1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and more specifically to a nonvolatile memory cell and its method of fabrication.
2. Discussion of Related Art
A conventional electrically erasable nonvolatile memory cell 100 is shown in FIG. 1. Memory cell 100 includes an n+ polysilicon floating gate 102 formed on the tunnel oxide 104 which is formed on the p-type silicon region 106. An interpoly dielectric 108 is formed on the n+ polysilicon floating gate and a control gate 110 formed on the interpoly dielectric layer 108 and a pair of n+ source/drain regions 109 are formed along laterally opposite sidewalls of floating gate electrode 102. Memory cell 100 includes fully landed metal contacts 120 which are formed entirely on the source/drain regions. To store information in memory device 100 charge is stored on floating gate 102. To erase memory device 100 charge is removed from floating gate 102.
A problem with memory storage cell 100, shown in FIG. 1, is that it has become difficult to further scale down its width and length to form smaller area cells and higher density memory circuits. For example, using contacts which are fully landed on diffusion requires a wider diffusion spacing than required for the memory cell transistor. Fully landed contacts require a large contact to gate and isolation spacing. Fully landed contacts prevent the reduction of both cell width and length. Additionally, floating gate 102 is formed by standard lithographic techniques with the cell width being limited by the minimum space resolution and the minimum registration. Another problem with cell 100 is that it suffers from charge leakage whereby electrons leak off the floating gate. In order to prevent charge leakage, the source junction is typically heavily graded leading to large under diffusion and a long gate length. Charge leakage also requires product level device optimization of voltages for balancing adequate read current verses charge loss margins thereby creating complexities in circuit design. Additionally, prevention of charge leakage also requires relatively thick tunnel oxides which in turn prevents the scaling of the device gate length. and length. Additionally, floating gate 102 is formed by standard lithographic techniques with the cell width being limited by the minimum space resolution and the minimum registration. Another problem with cell 100 is that is suffers from charge leakage whereby electrons leak off the floating gate. In order to prevent charge leakage, the source junction is typically heavily graded leading to large under diffusion and a long gate length. Charge leakage also requires product level device optimization of voltages for balancing adequate read current verses charge loss margins thereby creating complexities in circuit design. Additionally, prevention of charge leakage also requires relatively thick tunnel oxides which in turn prevents the scaling of the device gate length.